Rajagiri Notice

Notice No:  RSET/PL/N/6660                                                Date : 10/10/2022

    

 

Department of Electronics & Communication Engineering

 

Third Semester B.Tech Degree External Lab Examination (Supplementary), October 2022

 

 

 

 

100902/EC322T: LOGIC DESIGN LAB

 

Venue: Logic Design Lab, 2nd Floor, Main Block

 

Date

Time

Register No.

13-10-2022

Thursday

   09:30 a.m. – 12:30 p.m.

 

U2001122, U2001132, U2001133, U2001135, U2001154, U2001099 (6 Nos)

 

 

 

 

 

PRINCIPAL



Principal
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