Rajagiri Notice

Notice No:  RSET/PL/N/6660                                                Date : 10/10/2022

    

 

Department of Electronics & Communication Engineering

 

Third Semester B.Tech Degree External Lab Examination (Supplementary), October 2022

 

 

 

 

100902/EC322T: LOGIC DESIGN LAB

 

Venue: Logic Design Lab, 2nd Floor, Main Block

 

Date

Time

Register No.

13-10-2022

Thursday

   09:30 a.m. – 12:30 p.m.

 

U2001122, U2001132, U2001133, U2001135, U2001154, U2001099 (6 Nos)

 

 

 

 

 

PRINCIPAL



Principal
Sl No. Date Previous Notices
751 27-Oct-2022 Commencement of classes
752 27-Oct-2022 B.Tech. Minor Registration
753 27-Oct-2022 Blessing Ceremony of Sycamore Labs(Artificial Intelligence Lab)
754 27-Oct-2022 Academic Calendar for Academic Year 2022-2023
755 22-Oct-2022 RSET NDLI Executive Committee for the academic year 2022 - '23
756 22-Oct-2022 Seminar on 'Full Stack Web Development'
757 22-Oct-2022 Seminar on 'Full Stack Web Development'
758 21-Oct-2022 The final date of payment of college fees will be 30th October-2022.
759 20-Oct-2022 Winners of Poster Competition on Mental Health & Well-being
760 15-Oct-2022 Entering into the realm of AI
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