CALL FOR RESEARCH STAFF/PH. D POSITION
for a funded project under Chip to Startup Program,
Ministry of Electronics and Information Technology, Govt. of India
Position description: This project aims to develop a VLSI semiconductor component along with its software framework which will be an integral part of a video analysis system designed for autonomous classification and anomaly detection in real time video streams from CCTV cameras. This position is to develop the software framework which has to be integrated with the VLSI semiconductor component.
Applications are invited from interested and motivated candidates for Junior/ Senior Research Fellow positions on contractual basis as per the following details:
* Selected candidates with M.E/M.Tech/B Tech (with CGPA of 7.75 or above) willing to pursue full time PhD program under APJAKTU will be given preference. Such candidates have to apply at APJ Abdul Kalam Technological University (KTU), Kerala’s Ph. D research registration portal at https://app.ktu.edu.in/eu/anon/researchRegistration.htm before June 30th.
How to Apply:
Applications along with updated CV should be sent through mail to: jobinka@rajagiritech.edu.in & jaisonmpaul@rajagiritech.edu.in.
Shortlisted candidates will be informed for the interview.
CALL FOR PROJECT STAFF POSITIONS
for a funded project under Chip to Startup Program,
Ministry of Electronics and Information Technology, Govt.of India
Applications are invited from interested and motivated candidates for Junior/ Senior Research Fellow positions on contractual basis as per the following details:
Project Title : |
A RISC V based hardware accelerator for anomaly detection in autonomous security systems |
Junior/ Senior Research Fellow |
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Number of Vacancy |
2 positions |
Duartion |
1 year ( maybe extended to 3 years) |
Qualification |
A candidate with M.E/ M. Tech with specialisation in VLSI / Embedded Systems or B.E/ B. Tech. in ECE/EEE or PhD holders may apply. |
Skills required |
The candidate should be highly proficient with digital design using Verilog /VHDL, basic programming in any language and should possess good understanding of FPGA design flow. |
Age Limit |
As per MEITY, Govt. of India norms |
Remuneration |
SRF : Rs.35,000/- + HRA |
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Experience in working with embedded development boards is highly desirable for all candidates. Selected candidates with M.E/M.Tech/B Tech (with CGPA of 7.75 or above) willing to pursue full time PhD program under APJAKTU will be given preference. Such candidates have to apply at KTU Ph. D research registration portal at https://app.ktu.edu.in/eu/anon/researchRegistration.htm before June 30th.
How to Apply:
Applications along with updated CV should be sent through mail to jobinka@rajagiritech.edu.in. Shortlisted candidates will be informed for the interview.
Application Deadline: 30th June 2023.
Contact Email: jobinka@rajagiritech.edu.in.